1. Field of the Invention
The present invention relates to a system and an apparatus for designing layout of a LSI (large-scale-integrated circuit).
2. Description of the Related Art
A computer-aided design (CAD) system is often used in designing a semiconductor device such as a LSI. In the designing process using the CAD system, automatic layout design is performed based on the arrangement of circuits or information concerning connection between circuits to thereby determine the positions of respective circuits or interconnection route between circuits on the semiconductor device. After completion of the layout design, verification is made to ascertain whether or not the timing constraint between circuits is satisfied or whether or not power dissipation falls within the predetermined limit in the designed layout. If it has been determined that the timing constraint between circuits is not satisfied or that the power dissipation does not fall within the predetermined limit in the verification, the layout is redesigned to change the arrangement of the circuits.
As a LSI layout method for realizing a low power dissipation while satisfying the timing constraint of the LSI, techniques such as described in Patent Publication JP-11-67925-A are known. In the technique of patent publication, a simulation is performed after completion of the layout design based on an instructed test pattern to thereby obtain signal interconnects effective for reducing the power dissipation. Layout modification is made to the thus obtained signal interconnects to reduce the interconnect length, thereby further reducing the power dissipation. After completion of the layout change, timing analysis is performed to make layout modification once again for a part in which timing error has been detected. Such layout design is performed in the technique of the patent publication to realize an LSI layout achieving a low power dissipation while satisfying a required operating frequency.
As described above, in the technique of the above patent publication, designed layout is changed so as to satisfy a low power dissipation property and, thereafter, another layout change is performed in order to correct the timing error resulting from the layout change. Thus, the layout change is performed twice, involving a longer processing time. Further, in some LSI layouts, there is a case where an interconnect effective for reducing the power dissipation and another interconnect which is likely to undergo the timing error are connected to the same cell or circuit. In such a case, when the error correction is performed using only the timing as criterion, even though there is a solution satisfying both the timing and the reduction in the power dissipation, the length of the interconnect effective for reducing the power dissipation is likely to increase, with the result that a sufficient effect of reduction in the power dissipation cannot be obtained.